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IDProjectCategoryView StatusLast Update
0000868K18X001.00 SKB SWANHWpublic2021-12-23 19:29
Reporter(ALTech) Lonnie Kim Assigned To(HW) Sean Chiang Due Date2020-08-07 21:31
PriorityhighSeveritys2-severeReproducibilityalways
Status closedResolutionfixed 
Summary0000868: [SWAN]Request to ready HDMI equalizer on TMDS lines
DescriptionDear Sean

I think SWAN would be failed eye pattern diagram because patterns are too long.
Please ready to HDMI equalizer on TMDS lines.
Development schedule are very tight, so we need to estimate about problems.

Best regards

Lonnie Kim
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User List (ALTech) Juyoung Park , (ALTech) Lonnie Kim , (ALTech) SH Son , (ALTech) SY Yoon , (ALTech) Wooshin Kang , (HW) Tom Lee , (RD) Fu-chiang Young

Activities

(HW) Sean Chiang

2020-08-03 22:04

developer   ~0003926

Hi Lonnie,

Are you talking about the layout trace length control of TMDS signal?

Regards,
Sean

(ALTech) Lonnie Kim

2020-08-04 09:47

developer   ~0003935

Dear Sean

No, I worried about failed eye pattern at signal integrity.
So, I recommended buffer IC as like equalizer.
Could you provide real pattern length and Synaptics specification?

Best regards

Lonnie Kim

(HW) Sean Chiang

2020-08-05 19:20

developer   ~0003946

Dear Lonnie,

Yesterday we have discussed with Synaptics on the issue of the long trace length of HDMI.
According to Synaptics RD, the only problem is that when the box uses a long HDMI cable (for example, longer than 10M), it may cause a bad signal at far-end side, but a short HDMI cable should be no problem (for example, 1.5~2M)
Currently, Synaptics RD is checking this issue internally and will give us their advice before noon tomorrow.
Will let you know if there is any update tomorrow.

Thanks,
Regards,
Sean

(ALTech) Lonnie Kim

2020-08-06 10:37

developer   ~0003949

Dear Sean

I received below information about HDMI and USB pattern requirement from Synaptics Korea.
Please check with your PCB routing then feedback to me.

we have Max length requirement for HDMI and USB. For DDR, Customer should copy our reference layout.

HDMI.Routing
        14 Target impedance 100 ohms differential
    15 Minimum gap between differential pair and other signals 17.5 mils
    16 Trace length from SoC to ESD component 2.50 inches maximum
    17 Trace length from ESD component to HDMI connector 0.25 inches maximum
    18 Trace Length Match within diff. pair (p to n) : ±40mil
    19 Trace Length Match between diff. pairs : ±100mil
    21 Traces breaking in and out of ESD and connector must be symmetrical.
    22 Void reference plane below large pads of the ESD and CM choke, as recommended by the component manufacturer

USB Routing
        30 Target impedance 90 ohms differential
    31 Minimum gap between differential pair 10 mils
    32 Trace Length From SoC to CM choke : 6 inches maximum
    33 Trace Length From CM choke to connector : 1 inches maximum
    34 Trace Length Match within diff. pair (p to n) To within ±40 mil
    35 Preferably no via from the SoC to the USB connector. The number of vias for the two signals must be the same.
    36 Do not route USB traces under crystals, oscillators, clock synthesizers, magnetic devices or ICs that use or duplicate clocks.

Best regards

Lonnie Kim

(HW) Sean Chiang

2020-08-07 12:27

developer   ~0003958

Hi Lonnie,

Thanks for your information.
Actually, we have worked with Synaptics China team to review the layout a few weeks ago and definitely we will follow Synaptics's layout rule and requirement for the DDR, HDMI and USB. These suggestion you provided are the same as comment provided by Synaptics China ,and also are the common layout rule based on our experience.

Regards,
Sean

(ALTech) Lonnie Kim

2020-08-07 14:28

developer   ~0003960

Dear Sean

Okay. Good.
What is your next step?

Best regards

Lonnie Kim

(ALTech) Lonnie Kim

2020-08-10 08:20

developer   ~0003968

Dear Sean

You can check pattern routing length using layout program.
Please update ASAP.

Best regards

Lonnie Kim

(HW) Sean Chiang

2020-08-10 11:48

developer  

(HW) Sean Chiang

2020-08-10 11:48

developer   ~0003980

Hi Lonnie,

Please refer attached for the layout comment from Synaptics.
Please note that there is no requirement for the trace length from SoC to ESD components. Thanks.

============================================================================
 16 Trace length from SoC to ESD component 2.50 inches maximum
============================================================================

(HW) Sean Chiang

2020-08-21 09:43

developer   ~0004102

Hi Lonnie,

Have checked with Synaptics China team and send information of TI redirver IC "tmds181" to Synaptics review but haven't got response yet.
Will ask Synaptics to feedback on this asap and keep you posted once there's any update from Synaptics. Thanks.

Regards,
Sean

(HW) Sean Chiang

2020-08-28 10:06

developer   ~0004156

Hi Lonnie,

We have discussed with Synaptics China team yesterday and they think that the TI tmds181 is OK as HDMI redriver used with Synaptics VS550.

Regards,
Sean

Issue History

Date Modified Username Field Change
2020-08-03 20:42 (ALTech) Lonnie Kim New Issue
2020-08-03 20:42 (ALTech) Lonnie Kim Status new => assigned
2020-08-03 20:42 (ALTech) Lonnie Kim Assigned To => (HW) Sean Chiang
2020-08-03 20:43 (ALTech) Lonnie Kim Issue Monitored: (ALTech) Wooshin Kang
2020-08-03 20:43 (ALTech) Lonnie Kim Issue Monitored: (ALTech) SY Yoon
2020-08-03 20:44 (ALTech) Lonnie Kim Issue Monitored: (ALTech) Lonnie Kim
2020-08-03 20:44 (ALTech) Lonnie Kim Issue Monitored: (ALTech) Juyoung Park
2020-08-03 20:46 (ALTech) Lonnie Kim Issue Monitored: (ALTech) SH Son
2020-08-03 21:56 (HW) Sean Chiang Issue Monitored: (HW) Tom Lee
2020-08-03 21:57 (HW) Sean Chiang Issue Monitored: (RD) Fu-chiang Young
2020-08-03 22:04 (HW) Sean Chiang Note Added: 0003926
2020-08-04 09:47 (ALTech) Lonnie Kim Note Added: 0003935
2020-08-05 19:20 (HW) Sean Chiang Note Added: 0003946
2020-08-06 10:37 (ALTech) Lonnie Kim Note Added: 0003949
2020-08-07 12:27 (HW) Sean Chiang Note Added: 0003958
2020-08-07 14:28 (ALTech) Lonnie Kim Note Added: 0003960
2020-08-10 08:20 (ALTech) Lonnie Kim Note Added: 0003968
2020-08-10 11:48 (HW) Sean Chiang File Added: Synaptics layout comment for HDMI trace.png
2020-08-10 11:48 (HW) Sean Chiang Note Added: 0003980
2020-08-21 09:43 (HW) Sean Chiang Note Added: 0004102
2020-08-28 10:06 (HW) Sean Chiang Note Added: 0004156
2020-11-13 11:18 (SW) Jacky Chiang Project T99X171.00 SKB Eagle => K18X001.00 SKB SWAN
2021-12-23 19:29 (HW) Sean Chiang Status assigned => closed
2021-12-23 19:29 (HW) Sean Chiang Resolution open => fixed